Modern IGBT and SiC power modules can switch hundreds of amperes in a fraction of a microsecond. That speed enables compact, efficient power converters, but it also makes every millimeter of the current path important.
Conductors that appear to be simple connections on a schematic have inductance in the physical circuit. During fast switching, this parasitic, or stray, inductance can generate voltage overshoot, ringing, electromagnetic interference and additional switching loss. If it is not controlled, it can also overstress semiconductor devices and complicate parallel operation.
Parasitic inductance cannot be eliminated completely. It can, however, be understood, estimated and minimized through coordinated module selection, mechanical design, PCB layout, busbar design and gate-drive engineering.
What is parasitic inductance?
Any conductor carrying current produces a magnetic field. When that current changes, energy is stored in or released from the magnetic field. This behavior gives the conductor inductance even when no discrete inductor appears in the schematic.
Parasitic inductance is present in:
- Power-module terminals
- Internal module connections
- DC busbars
- PCB traces and planes
- Capacitor leads and terminals
- Cable connections
- Fuse and contactor paths
- Gate-drive connections
- Current sensors
- Snubber circuits
The most important value is usually the total inductance of a current loop, not the inductance of one conductor considered in isolation. Both the outgoing and return paths determine the loop area and magnetic flux.
Fuji Electric’s IGBT application guidance identifies representative stray inductances throughout practical inverter systems and explains how those inductances interact with circuit capacitances to create resonant behavior and electromagnetic emissions.
Why a few nanohenries matter
The voltage generated across an inductance is described by:
[
V_L = L\frac{di}{dt}
]
where:
- (V_L) is the inductive voltage
- (L) is the parasitic inductance
- (di/dt) is the rate of current change
Consider a switching loop with 40 nH of total parasitic inductance. If current changes at 5,000 A/µs, the inductive voltage is:
[
V_L = 40\text{ nH} \times 5{,}000\text{ A/µs} = 200\text{ V}
]
That voltage appears in addition to, or subtracts from, the circuit voltage according to its polarity and location. In a high-voltage converter, an extra 200 V can consume a significant part of the semiconductor’s voltage margin.
The problem becomes more pronounced with faster devices. SiC MOSFETs can switch at substantially higher (di/dt) and (dv/dt) than conventional silicon devices. A layout that performed acceptably with an older IGBT may produce excessive overshoot or ringing after a faster device is substituted.
The main effects of parasitic inductance
Turn-off voltage overshoot
When a semiconductor interrupts current, the energy stored in the commutation-loop inductance must go somewhere. It produces a voltage rise across the switching device.
The peak device voltage can be approximated as:
[
V_{\text{peak}} \approx V_{\text{DC}} + L_\sigma\frac{di}{dt}
]
This simplified relationship does not capture every dynamic effect, but it clearly shows why DC-link voltage, loop inductance and switching speed must be evaluated together.
Fuji Electric’s SiC module application guidance illustrates that turn-off surge voltage rises as stray inductance increases under otherwise comparable conditions.
Excessive overshoot can approach or exceed the module’s rated blocking voltage, reducing reliability or causing immediate failure.
Ringing
Parasitic inductance combines with device output capacitance, junction capacitance, bus capacitance and other stray capacitances to form resonant circuits.
The approximate resonant frequency is:
[
f_r = \frac{1}{2\pi\sqrt{LC}}
]
Fast switching can excite these resonances, producing high-frequency oscillation in voltage and current. Ringing can:
- Increase peak voltage
- Produce false gate transitions
- Increase switching loss
- Create conducted and radiated emissions
- Interfere with sensing and control circuits
- Complicate waveform measurement
Fuji Electric provides an example in which 200 nH of stray inductance and 500 pF of capacitance create a resonance near 16 MHz.
Gate-voltage disturbance
Inductance in the common emitter or common source path is particularly important. Power current flowing through this inductance creates a voltage that appears in the gate-drive loop.
The resulting feedback can:
- Reduce effective gate voltage during turn-on
- Slow or distort switching
- Produce gate-voltage spikes
- Encourage parasitic turn-on
- Create oscillation
- Cause unequal switching in parallel devices
This is why modules with Kelvin emitter or Kelvin source terminals can offer a major advantage. The gate driver references a low-current auxiliary terminal rather than the high-current power path, reducing the influence of common-path inductance.
Increased switching loss
Designers often slow a device with more gate resistance to control overshoot caused by excessive inductance. This can reduce (di/dt) and (dv/dt), but it also increases switching time and energy loss.
Low-inductance construction allows the semiconductor to switch closer to its intended capability without violating voltage or electromagnetic-compatibility limits.
Fuji Electric’s recent three-dimensional wiring development for SiC power modules reduced internal parasitic inductance by approximately 70% compared with the company’s conventional structure and produced an approximately 50% reduction in switching loss under the evaluated conditions.
Unequal current sharing
In parallel module arrangements, unequal inductance can cause different transient voltages and switching speeds in each branch. One module may temporarily carry more current or experience greater switching stress.
A design with equal DC, AC and gate-path resistance but unequal inductance may still share current poorly during switching. Physical symmetry matters as much as schematic symmetry.
Identify the critical current loops
The first step in controlling inductance is to identify where current commutates during each switching transition.
In a typical half-bridge, the high-frequency commutation loop includes:
- The local positive DC-link capacitor terminal
- The upper or lower switching device
- The complementary diode or MOSFET channel
- The negative DC-link capacitor terminal
- The conductors connecting these elements
The bulk capacitor located elsewhere in the enclosure may stabilize the average DC bus, but it cannot supply the fastest current edges effectively if long busbars or cables separate it from the module. A low-inductance local capacitor path is therefore essential.
Other critical loops include:
- Gate turn-on loop
- Gate turn-off loop
- Active-clamp loop
- Desaturation-detection loop
- Snubber loop
- Current-sensor path
- Common-mode return path
Each loop should be evaluated independently. Reducing the power-loop inductance does not automatically correct a long or poorly referenced gate-drive loop.
Minimize the commutation-loop area
Loop inductance is strongly related to enclosed area. The basic design principle is to keep the outgoing and return current paths close together.
Effective techniques include:
- Use overlapping positive and negative conductors.
- Place laminated busbar layers close together.
- Use broad copper planes rather than long, narrow traces.
- Position the DC-link capacitor close to the module terminals.
- Avoid unnecessary bends and detours.
- Keep connections short and direct.
- Use several parallel connection points where appropriate.
- Avoid large gaps between forward and return paths.
A wide conductor alone is not necessarily low inductance. If its return path is distant, the overall loop can still have substantial inductance. Closely coupled forward and return conductors produce opposing magnetic fields, reducing external flux and loop inductance.
Place DC-link capacitors close to the module
At the switching frequency and its harmonics, the effective DC-link capacitor is the one connected through the lowest-inductance path.
A practical DC link may use:
- Bulk electrolytic capacitors for energy storage
- Film capacitors for high-frequency current
- Small local capacitors for the fastest switching components
The local film or ceramic capacitor should be mounted as close as practical to the module’s DC terminals. Its terminals and connection structure are part of the loop, so a low-inductance capacitor connected through long leads may not provide a low-inductance result.
Evaluate:
- Capacitor equivalent series inductance
- Terminal geometry
- Connection length
- Busbar overlap
- RMS ripple-current capability
- Voltage rating
- Temperature
- Lifetime
- Fault-current behavior
Do not choose a capacitor by capacitance alone. Its impedance across the relevant frequency range is what determines its effectiveness during switching.
Use laminated or closely coupled busbars
A laminated busbar places positive and negative conductors in parallel layers separated by thin insulation. This arrangement reduces loop area and provides strong magnetic-field cancellation.
Good busbar design should:
- Keep the layers close
- Maintain overlap up to the module terminals
- Avoid narrow necks
- Minimize terminal extensions
- Use symmetrical paths to parallel modules
- Position capacitor connections directly across the DC layers
- Meet creepage, clearance and insulation requirements
Electrical, thermal and mechanical requirements must be resolved together. A very compact busbar still needs adequate insulation, current capacity, cooling and fault withstand.
Three-dimensional electromagnetic simulation can help compare geometries before tooling is committed.
Choose a low-inductance module package
Some inductance exists inside the module and cannot be corrected by external layout. Package architecture therefore matters.
Review the manufacturer’s data for:
- Internal stray inductance
- Terminal arrangement
- Kelvin emitter or source availability
- Module topology
- Recommended busbar arrangement
- Recommended capacitor placement
- Switching test conditions
- Package scalability for parallel operation
Fuji Electric’s 7th-generation X-Series IGBT modules combine lower-loss semiconductor technology with lower-inductance package designs.
Selecting a module with terminals that naturally support a compact commutation loop may be more effective than trying to correct an unfavorable geometry with a complicated external busbar.
Separate the power and gate-drive paths
The gate driver should connect to the module through a small, dedicated loop.
Recommended practices include:
- Place the driver close to the module.
- Use the Kelvin emitter or source terminal where provided.
- Route gate and return conductors together.
- Keep the gate loop away from high-(dv/dt) nodes.
- Avoid sharing the power-emitter or power-source path.
- Use compact, low-inductance gate resistors.
- Separate turn-on and turn-off paths when useful.
- Place clamping and protection components at the gate terminals.
- Maintain suitable isolation and creepage distances.
The loop between the driver’s decoupling capacitor, output stage, gate and return terminal also matters. A short connection to the gate terminal is not enough if the driver’s local supply loop is large.
For high-side devices, account for the isolation barrier, common-mode transient immunity and the parasitic capacitance of the isolated power supply.
Control common emitter or source inductance
Common-path inductance is shared by the load-current loop and the gate-drive return. Its induced voltage acts as feedback on the gate signal.
To reduce it:
- Use a module with an auxiliary emitter or source terminal.
- Connect the driver return directly to that terminal.
- Do not route gate-return current through the power busbar.
- Keep the auxiliary connection short.
- Avoid coupling the gate-return trace to the switching node.
- Follow the module manufacturer’s recommended terminal connections.
An oscilloscope measurement referenced to the wrong emitter or source point can also hide the true gate voltage seen by the chip. Measure gate voltage at the designated auxiliary terminal whenever possible.
Design parallel connections symmetrically
For parallel modules, symmetry should be maintained from the capacitor bank through the modules and into the load connection.
Match:
- Positive-bus inductance
- Negative-bus inductance
- Output-path inductance
- Gate-loop inductance
- Gate resistance
- Driver propagation delay
- Module temperature
- Contact resistance
A star connection is not automatically symmetrical at high frequency. The physical length, width, layer spacing and mutual coupling of each branch must be comparable.
Individual gate resistors are generally preferable to one common resistor. Depending on the module and application, separate drivers or carefully matched driver outputs may be required.
Fuji Electric provides dedicated application guidance for parallel IGBT-module operation as part of its power-module design resources.
Use snubbers as a refinement, not a substitute for layout
An RC, RCD or capacitor snubber can absorb switching energy or damp an unwanted resonance. It can be valuable when properly designed, but it should not be used to compensate for avoidable busbar inductance.
A snubber must have its own low-inductance connection. If it is mounted far from the switching loop, its leads may prevent it from controlling the fastest transient.
When designing a snubber, consider:
- Circuit topology
- Target resonant frequency
- Peak current
- Pulse-energy rating
- Capacitor inductance
- Resistor pulse capability
- Thermal dissipation
- Physical placement
First reduce the source of the inductance. Then use measured waveforms or simulation to size damping components.
Tune the gate drive after optimizing the layout
Gate resistance is an important tool for balancing switching loss, overshoot, diode recovery and electromagnetic emissions. It should be tuned on the final mechanical layout or a representative prototype.
Increasing turn-off gate resistance can reduce (di/dt) and overshoot, but it generally increases turn-off loss. Increasing turn-on resistance can reduce diode-recovery stress and (dv/dt), but it increases turn-on loss.
Other techniques may include:
- Separate turn-on and turn-off resistors
- Multilevel gate drive
- Active gate control
- Miller clamping
- Negative turn-off bias
- Active clamping
These features do not eliminate the need for low inductance. They work best when the underlying layout is already controlled.
Do not copy gate-resistor values from a different test fixture without validation. Module current, DC voltage, temperature, driver impedance and parasitic inductance all influence the result.
Pay special attention to SiC modules
SiC MOSFETs reward low-inductance design but expose layout weaknesses quickly.
Important considerations include:
- Very high (dv/dt) and (di/dt)
- Lower gate-voltage tolerance than some IGBTs
- Potential parasitic turn-on
- High-frequency ringing
- Sensitivity to common-source inductance
- Driver common-mode transient immunity
- Short-circuit protection speed
- Measurement bandwidth and probe quality
A converter should not be upgraded from IGBT to SiC by changing the module alone. The busbar, capacitors, gate driver, protection circuits, cooling and PCB layout should be reevaluated as a system.
Fuji Electric has developed low-inductance SiC packaging structures using compact current paths and copper-pin or three-dimensional interconnection technologies to support higher power density and faster switching.
Model inductance before building hardware
Several levels of analysis are available.
Hand calculations
Basic loop geometry and the relationship (V=L(di/dt)) provide valuable early estimates. They can show whether a proposed inductance is compatible with the device’s voltage margin.
Circuit simulation
Add estimated parasitic inductances to the switching model. Separate the inductance into meaningful elements, such as:
- DC-positive path
- DC-negative path
- Module internal path
- Capacitor connection
- Common emitter or source
- Gate path
- Load connection
One lumped inductance may reproduce voltage overshoot but will not reveal how different locations affect gate behavior or common-mode noise.
Electromagnetic extraction
Finite-element or partial-element-equivalent-circuit tools can extract self and mutual inductance from the actual PCB or busbar geometry. This is particularly valuable for laminated busbars, parallel modules and high-current SiC converters.
Simulation accuracy still depends on realistic device models, capacitor characteristics, terminal geometry and boundary conditions. Prototype testing remains necessary.
Measure without creating misleading waveforms
Fast power-module waveforms are easy to measure incorrectly. Probe inductance, ground leads and poor connection points can create ringing that is not present in the actual circuit, or hide ringing that is.
Use:
- A high-bandwidth differential probe with an adequate voltage rating
- A current probe with suitable bandwidth and current capability
- Short probe connections
- Manufacturer-recommended probe points
- A compact gate-voltage probe loop
- Proper oscilloscope isolation and grounding practices
- Deskew between voltage and current channels when calculating switching energy
Never use a conventional grounded oscilloscope probe on a high-side switching node unless the measurement method is explicitly designed and rated for it.
For gate voltage, measure directly between the gate and Kelvin emitter or source terminals. For device voltage, connect as close as practical to the relevant module terminals.
The measurement setup should be documented so results can be reproduced.
Validate with a double-pulse test
A double-pulse test allows engineers to evaluate switching behavior at controlled current, voltage and temperature.
It can reveal:
- Turn-on and turn-off energy
- Voltage overshoot
- Current overshoot
- Diode reverse recovery
- Ringing frequency
- Gate-voltage disturbance
- Parasitic turn-on
- Effect of gate resistance
- Effect of snubber components
Test across the intended operating envelope, including:
- Maximum DC-link voltage
- Representative and maximum current
- Minimum and maximum junction temperature
- Production component tolerances
- Expected gate-supply variation
The final voltage margin should account for measurement uncertainty and abnormal operating conditions, not only a nominal laboratory waveform.
Estimating loop inductance from a waveform
If the current fall rate and inductive voltage contribution can be identified, total loop inductance can be approximated from:
[
L_\sigma \approx \frac{\Delta V}{di/dt}
]
For example, if the inductive overshoot is 120 V while current changes at 4,000 A/µs:
[
L_\sigma \approx \frac{120}{4{,}000} = 0.03\text{ µH} = 30\text{ nH}
]
This is a simplified estimate. Device capacitance, diode recovery, nonlinear switching behavior and measurement error can affect the result. It is still useful for comparing prototypes and validating simulation trends.
Ringing frequency can also help estimate the combined LC network if either the effective inductance or capacitance is already known.
A practical low-inductance design checklist
Before releasing a power converter design, confirm:
- Have all high-frequency commutation loops been identified?
- Is the local DC-link capacitor adjacent to the module terminals?
- Are positive and negative conductors closely overlapped?
- Are busbar necks, standoffs and terminal extensions minimized?
- Does the module package support a compact external loop?
- Are Kelvin emitter or source terminals used correctly?
- Is the gate driver close to the module?
- Is the driver-supply decoupling loop compact?
- Are high-(dv/dt) nodes separated from gate and sensing circuits?
- Are parallel power and gate paths physically symmetrical?
- Are snubbers connected through genuinely low-inductance paths?
- Have parasitic elements been included in simulation?
- Have critical inductances been extracted from the physical geometry?
- Has the design been verified with a double-pulse test?
- Were waveforms measured using low-inductance probe connections?
- Is adequate voltage margin maintained at maximum current, voltage and temperature?
- Have switching loss, EMI and reliability been evaluated together?
Low inductance begins with the physical design
Parasitic inductance is not a minor correction to an otherwise complete schematic. In a fast-switching power converter, the mechanical structure is part of the electrical circuit.
The most effective strategy is to select a suitable low-inductance power-module package, minimize the commutation-loop area, place capacitors close to the module, separate gate and power paths, and validate the finished structure under realistic switching conditions.
Fuji Electric provides IGBT and SiC power modules, application manuals, technical documents and simulation resources to support converter design. Its 7th-generation X-Series modules feature lower-loss chip technology and low-inductance package options for industrial, renewable-energy, transportation and power-conversion applications.
By addressing parasitic inductance early, designers can reduce voltage stress and ringing while making better use of the switching performance available from modern power semiconductors.